A merged memory logic (MML) device is an integrated device that incorporates a memory cell array, such as a dynamic random access memory (DRAM), and an analog or a peripheral circuit into a single chip. Since multimedia functions have been enhanced by the introduction of the MML, it is possible to efficiently achieve integration and high-speed of semiconductor devices.
Development is underway for manufacturing a capacitor having high capacitance for an analog circuit in which high-speed operation is needed. There are two main types of capacitors used in analog circuits. They are polysilicon/insulator/polysilicon (PIP) type capacitors and metal/insulator/metal (MIM) type capacitors. In general, because conductive polysilicon is used for the upper and lower electrodes of a PIP type capacitor, a natural oxide forms due to an oxidation occurring at the interface between the upper/lower electrode and a dielectric thin layer. Because of the natural oxide formation, the conventional PIP capacitor has a defect that lowers its capacitance.
In addition, the capacitance decreases due to a depletion region formed on a polysilicon layer. Thus, there is a disadvantage in that the PIP capacitor is not suitable for high-speed and high-frequency operations. To overcome these disadvantages, a metal-insulator-silicon (MIS) or a metal-insulator-metal (MIM) is used. The MIM type capacitor is generally used for high performance semiconductor devices because it has low resistivity and does not cause parasitic capacitance derived from the depletion.
Hereinafter, a related art capacitor will be described with reference to the accompanying drawings.
FIG. 1 is a sectional view of showing a structure of a MIM capacitor according to the related art.
As shown in FIG. 1, a capacitor according to the related art includes a first interlayer dielectric 10 having the first contact hole formed on a substrate. A Metal-Insulator-Metal (MIM) type capacitor is formed at an upper portion of the first interlayer dielectric 10. The MIM type capacitor includes a first conductive layer 11, a first insulating layer 13, and a second conductive layer 14, which are sequentially deposited at an upper portion of the first interlayer dielectric 10. Here, a second interlayer dielectric 15 is formed on an entire surface of the substrate including the MIM type capacitor. The first conductive layer 11, functioning as a lower electrode of the capacitor, is connected to a third conductive layer 17a formed on the second interlayer dielectric 15 through a first plug 16, which is formed in a second contact hole.
In addition, the second conductive layer 14, functioning as an upper electrode of the capacitor, is connected to a fourth conductive layer 17b formed on the second interlayer dielectric 15 through a second plug 20, which is formed in a third contact hole
In the capacitor according to the related art, a first conductive layer 11, a first insulating layer 13, and a second conductive layer 14 are flatly constructed of layers in horizontal planes. In order to increase the capacitance through increasing the surface area of the electrodes, the related art capacitor is expanded along the horizontal plane.
Accordingly, in the capacitor according to the related art, there is a limit to increasing the length and width of a capacitor with a defined area.